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Energy-efficient computing is a much needed technological advantage for future. Approximate or inexact computing is a computing paradigm that can trade energy and computing time with accuracy of output. Recent years have seen a lo...
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Energy-efficient computing is a much needed technological advantage for future. Approximate or inexact computing is a computing paradigm that can trade energy and computing time with accuracy of output. Recent years have seen a lot of researches in industry as well as aca-demia. The aim of these researches is to fruitfully realize the dream of a greener and energy-efficient computing era. This paper presents a comprehensive and concise survey of the current research trends and contributions in energy-efficient computing from computational point of view. Recent developments in approximate computing hardware, software and approximate data communication have also been discussed in this article.
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ABSTRACT The number of smart devices grows rapidly, and the main leakage of many of these devices is their limited batteries, in addition to the need for a fast and low-power computing system. Approximate calculations are an excel...
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ABSTRACT The number of smart devices grows rapidly, and the main leakage of many of these devices is their limited batteries, in addition to the need for a fast and low-power computing system. Approximate calculations are an excellent method for such systems to achieve higher speed and less area and power consumption at the cost of lower accuracy. Furthermore, in many applications with inherent tolerance for insignificant inaccuracies such as image processing, approximate computing can be used to achieve acceptable performance with higher speed, lower power or area consumption. In this work, approximate multiplier structures are proposed based on working on the partial product trees with the aim of reducing area consumption and increasing accuracy. Comprehensive experimental analysis is performed to evaluate the performance of the proposed multiplier in terms of area, delay, power consumption, and accuracy. The results show that our suggested design improves at most 29% of power consumption, 11% of delay, and 55% of the area rather than an exact multiplier. Moreover, the performance of our multipliers is investigated based on the peak signal noise ratio (PSNR) for processing two images, which lead to 56.65 and 23.6 dB.
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Approximate triple modular redundancy (ATMR) is sought for logic masking of soft errors while effectuating lower area overhead than conventional TMR through the introduction of approximate modules. However, the use of approximate ...
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Approximate triple modular redundancy (ATMR) is sought for logic masking of soft errors while effectuating lower area overhead than conventional TMR through the introduction of approximate modules. However, the use of approximate modules instigates reduced fault coverage in ATMR. In this work, we target better design tradeoffs in ATMR by proposing a heuristic method that effectively utilizes a threshold for unprotected input vectors to generate good enough combinations of approximate modules for ATMR, which accomplishes higher fault coverage and reduced area overhead compared with previously proposed approaches. The key concept is to employ logic optimization techniques of prime implicant (PI) expansion and reduction for successively obtaining approximate modules such that the combination of three approximate modules appropriately functions as an ATMR. For an ATMR to function appropriately, blocking is used to ensure that at each input vector, through the prime implicant (PI) expansion and reduction technique, only one approximate module differ from the original circuit. For large circuits, clustering is utilized and comparative analysis indicates that higher fault coverage is attained through the proposed ATMR scheme while preserving the characteristic feature of reduced area overhead. With a small percentage of unprotected input vectors, we achieved substantial decrease in transistor count and greater fault detection, i.e., an improvement of up to 26.1% and 42.1%, respectively.
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With the increasing popularity of the Internet of Things and massive Machine Type Communication technologies, the number of connected devices is rising. However, although enabling valuable effects to our lives, bandwidth and laten...
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With the increasing popularity of the Internet of Things and massive Machine Type Communication technologies, the number of connected devices is rising. However, although enabling valuable effects to our lives, bandwidth and latency constraints challenge Cloud processing of their associated data amounts. A promising solution to these challenges is the combination of Edge and approximate computing techniques that allows for data processing nearer to the user. This article aims to survey the potential benefits of these paradigms' intersection. We provide a state-of-the-art review of circuit-level and architecture-level hardware techniques and popular applications. We also outline essential future research directions.
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Researchers have recently designed a number of application-specific fault tolerance mechanisms that enable applications to either be naturally resilient to errors or include additional detection and correction steps that can bring...
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Researchers have recently designed a number of application-specific fault tolerance mechanisms that enable applications to either be naturally resilient to errors or include additional detection and correction steps that can bring the overall execution of an application back into an envelope for which an acceptable execution is eventually guaranteed. A major challenge to building an application that leverages these mechanisms, however, is to verify that the implementation satisfies the basic invariants that these mechanisms require---given a model of how faults may manifest during the application's execution.To this end we present Leto, an SMT-based automatic verification system that enables developers to verify their applications with respect to an execution model specification. Namely, Leto enables software and platform developers to programmatically specify the execution semantics of the underlying hardware system as well as verify assertions about the behavior of the application's resulting execution. In this paper, we present the Leto programming language and its corresponding verification system. We also demonstrate Leto on several applications that leverage application-specific fault tolerance.
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Although approximate computing promises better performance for applications allowing marginal errors, dearth of hardware support and lack of run-time accuracy guarantees makes it difficult to adopt. We present As-Is, an Anytime Sp...
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Although approximate computing promises better performance for applications allowing marginal errors, dearth of hardware support and lack of run-time accuracy guarantees makes it difficult to adopt. We present As-Is, an Anytime Speculative Interruptible System that takes an approximate program and executes it with time-proportional approximations. That is, an approximate version of the program output is generated early and is gradually refined over time, thus providing the run-time guarantee of eventually reaching 100% accuracy. The novelty of our As-Is architecture is in its ability to conceptually marry approximate computing and speculative computing. We show how existing innovations in speculative architectures can be repurposed for anytime, best-effort approximation, facilitating the design efforts and overheads needed for approximate hardware support. As-Is provides a platform for real-time constraints and interactive users to interrupt programs early and accept their current approximate results as is. 100% accuracy is always guaranteed if more time can be spared. Our evaluations demonstrate favorable performance-accuracy tradeoffs for a range of approximate applications.
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The accuracy of an approximate computation is the distance between the result that the computation produces and the corresponding fully accurate result. The reliability of the computation is the probability that it will produce an...
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The accuracy of an approximate computation is the distance between the result that the computation produces and the corresponding fully accurate result. The reliability of the computation is the probability that it will produce an acceptably accurate result. Emerging approximate hardware platforms provide approximate operations that, in return for reduced energy consumption and/or increased performance, exhibit reduced reliability and/or accuracy.
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Emerging high-performance architectures are anticipated to contain unreliable components that may exhibit soft errors, which silently corrupt the results of computations. Full detection and masking of soft errors is challenging, e...
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Emerging high-performance architectures are anticipated to contain unreliable components that may exhibit soft errors, which silently corrupt the results of computations. Full detection and masking of soft errors is challenging, expensive, and, for some applications, unnecessary. For example, approximate computing applications (such as multimedia processing, machine learning, and big data analytics) can often naturally tolerate soft errors.
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Background: Approximate computing is an emerging trend in recent years that trades off the requirement of exact computation for the improvement of speed and power performance. Objective: Researchers are trying to improve the speed...
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Background: Approximate computing is an emerging trend in recent years that trades off the requirement of exact computation for the improvement of speed and power performance. Objective: Researchers are trying to improve the speed and power performance proposing different algorithms. Methods: This paper proposes approximate compressors used for the design of approximate multipliers. Results: By using the proposed method, approximate multipliers of different length have been synthesized and a comparative study with previously presented multipliers have been dealt here which shows that the proposed circuits have better speed and power. Conclusion: Finally, the proposed circuits have been used for image processing applications.
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Power consumption is a serious concern in the field of digital design. Reducing power supply voltage, power gating, transistor downscaling, voltage over scaling, applying modern technology and approximate computing are some candid...
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Power consumption is a serious concern in the field of digital design. Reducing power supply voltage, power gating, transistor downscaling, voltage over scaling, applying modern technology and approximate computing are some candidate means in reducing power consumption. Among these candidates, approximate computing can generate a trade-off between accuracy and power-delay-area efficiency in error resilient applications. According to Moore's law together with CMOS problems in nanoscale regime, modern technologies emerge to solve these problems. Among these recent technologies, CNTFET technology is considered as promising. As multiplication is frequently applied in multimedia processing, implementing efficient multipliers constitute critical. Compressors are fundamental elements in reduction tree multipliers and improve their efficiency, thus an improvement in multipliers' performance. A new 12-transistor approximate 4:2 compressor is proposed here. This new appropriate compressor, in terms of area, power consumption, accuracy and reliability design, is more efficient than its existing counterparts.
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